1. Field of the Invention
The present invention relates to a symbol used in a schematic capture program, and in particular to a multiple function symbol that is configurable during schematic capture.
2 Description of the Related Art
Embedding carry logic in high level components, such as counters, adders, and comparators, for schematic capture programs is well known in the art. For example, FIG. 1 illustrates one high level component, a counter 100, which is provided by a schematic capture symbol library which in turn is incorporated into an FPGA design program. Counter 100, which includes embedded carry logic, has been available to the end user only as a hard macro. A hard macro provides fully partitioned and placed design fragments, thereby optimizing performance for the end user.
However, irrespective of the desirability of known performance, unless this hard macro provides exactly the resources needed by the end user, certain inefficiencies occur. For example, assume the library of the schematic capture program includes 8- and 16-bit counter hard macros. If the end user needs a 10-bit counter, the end user must choose between using the 16-bit counter, thereby wasting 6 bits, or using the 8-bit counter, thereby necessitating the building of 2 extra bits. To build these two extra bits, the end user must access another program to create a new hard macro, and then use a translator to provide the new hard macro in the FPGA design program.
Because of the complexity of designing a new hard macro, a large library of commonly used hard macros is typically provided. However, each hard macro includes substantially the same underlying circuitry, thereby significantly increasing the space needed for the library. Moreover, after a hard macro is selected, it allows no access to its underlying logic, thereby undesirably preventing any simulation of the carry logic during schematic capture. Therefore, a need arises for a method which allows an end user to easily design a carry logic circuit, minimizes library space, and allows simulation during schematic capture.